1. Field of the Invention
The present inventions relates to a CCD (Charge Coupled Device)-type charge transfer device driven by two phase pulses and to a solid image pickup apparatus using such charge transfer devices, and in particular, relates to an improvement for increasing the charge transfer efficiency adjacent to an output portion of the charge transfer device.
2. Description of the Related Art
FIG. 6 is a diagram showing the structure of a general interline transfer-type solid image pickup apparatus. In FIG. 6, reference numeral 101 denotes a photodiode, 102 denotes a vertical CCD register which receives and transfers a charge from the photodiode 101, 103 denotes a horizontal CCD register which receives and transfers the charge from the vertical CCD register 102, 104 denotes a charge detection portion which detects the charge transferred from the horizontal CCD register 103, and 105 denotes an output amplifier. Here, a rectangular portion enclosed by a broken line shows a pixel 106.
For an image pickup apparatus used for a digital still camera such as a digital steal camera, reduction of the power consumption is indispensable. In the case of a two dimensional CCD image sensor, the power consumption of the horizontal CCD registers is particularly large, and the power consumption increases as the speed of the horizontal CCD registers increases. In order to reduce the power consumption, the reduction of the driving voltage of the horizontal CCD register is an critical problem to be solved.
One of the measures to solve the above-described problem is disclosed in Japanese Unexamined Patent Application, First Publication No. 11-17163. This disclosure involves a method in which, in a CCD-type register having two layered electrodes and a two phase driving system, generation of the potential drop under the boundary between two electrodes is suppressed by forming an n-type low concentration semiconductor layer in a self-aligning manner.
FIG. 7 is a plan view showing the structure of the output portion of the conventional horizontal CCD registers, and FIG. 8 shows a cross-sectional view along the line IIxe2x80x94II. As shown in FIG. 7, above the charge transfer channel 111, a plurality of storage electrodes 112a, 112b, 112c, . . . and a plurality of barrier electrodes 113a, 113b, 113c, . . . are formed. Here, to simplify the description, a pair of charge transfer electrodes composed of a storage electrode 112a and a barrier electrode 113a, disposed at the most left side of FIG. 7, is called horizontal terminal electrodes and the other pairs of charge transfer electrodes are simply called horizontal electrodes.
An output electrode 114 is disposed adjacent to the horizontal terminal storage electrode 112a. At one terminal of the output gate electrode 114, a floating diffusion layer 115, which constitutes a charge detection portion 104, is formed, and the floating diffusion layer 115 is connected to the output amplifier 105. At one side of the floating diffusion layer 115, a reset gate electrode 116 is provided, and at one side of the reset gate electrode 116, a reset drain 117 is provided. Each adjoining pair of storage electrodes 112a, 112b, 112c, . . . , and barrier electrodes 113a, 113b, 113c, . . . are connected to one metal wire 118 and the other metal wire 119 alternatively.
Two phase driving pulses xcfx86H1 and xcfx86H2 are respectively input into one metal wire 118 and the other metal wire 119. A direct-current (dc) voltage VOG is applied to the output gate 114, a reset pulse xcfx86R is input into the reset gate electrode 116, and a dc voltage VRG is applied to the reset drain 117.
Next, the cross-sectional structure shown in FIG. 8 is explained in the order of the manufacturing process. FIG. 9 shows a manufacturing method of the conventional charge transfer device. As shown in FIG. 9A, an nxe2x88x92-type semiconductor well 121 having an impurity concentration of 8xc3x971016 cmxe2x88x923 is formed with a thickness of 0.5 xcexcm on a p-type silicon substrate 120 having an impurity concentration of 1xc3x971015 cmxe2x88x923, and a first insulating film 122 is formed with a thickness of 100 nm on the surface of the nxe2x88x92-type semiconductor well 121 by an oxidation process such as thermal oxidization. Subsequently, as shown in FIG. 9B, a first polycrystalline silicon film is deposited with a thickness of 300 nm and the barrier electrodes 113a, 113b, 113c, . . . and the output gate electrode 114 and reset gate electrode 116 are formed by patterning the first polycrystalline silicon film.
Subsequently, as shown in FIG. 9C, an approximately 100 nm thick second insulating film 123 is formed on the nxe2x88x92-type semiconductor well 121 by an oxidation process such as thermal oxidization, and a third insulating film 124 is formed on the side surfaces of the barrier electrodes 113a, 113b, 113c, . . . , the output gate electrode 114, and the reset gate electrode 116 by an accelerating oxidation of the polycrystalline silicon. Subsequently, a resist film is coated thereon, a resist pattern 125 is formed by photolithography, and nxe2x88x92-type semiconductor regions 126a, 126b, 126c, . . . are formed by phosphorus ion implantation. Here, the first polycrystalline silicon layer and the third insulating layer serve as the mask for the ion implantation.
Subsequently, as shown in FIG. 9D, a 300 nm thick second polycrystalline silicon film is deposited and a plurality of charge electrodes 112a, 112b, 112c, . . . are formed by patterning the film using photolithography. Subsequently, as shown in FIG. 9E, an n+-type semiconductor region 127 having an impurity concentration of 1xc3x971020 cmxe2x88x923 is formed with a thickness of 0.3 xcexcm and then an interlayer insulating film 128 is formed. Subsequently, as shown in FIG. 9F, a through hole (not shown) is formed, an aluminum film (not shown) is deposited, and by patterning the aluminum film using photolithography, two metal conducive lines 118 and 119 are formed. The first polycrystalline silicon film, the second polycrystalline silicon, and n+-type semiconductor region 127 are respectively connected to those lines. The charge transfer device is obtained by the above-described manufacturing process, and the structure shown in FIG. 9F becomes the same as that shown in FIG. 8
As shown in FIG. 7, although the channel widths W1 of general CCD registers are 10 to 50 xcexcm, the channel width W2 in the vicinity of the horizontal terminal electrode is formed as narrow as 5 to 10 xcexcm. The reason for this narrow channel width is that it is necessary to minimize the area of the floating diffusion layer in order to increase the charge detecting sensitivity of the charge detection portion 104. In general when the channel width is formed narrower in the charge transfer direction, the transfer electric field decreases and the charge transfer efficiency decreases as the channel width becomes narrower.
FIG. 10 is a typical diagram showing a schematic potential distribution in the vicinity of the output portion of the conventional horizontal CCD register. This figure illustrates a case of charge transfer by two phase driving pulses xcfx86H1 and xcfx86H2. The signal charge is transferred from the right side to the left side of the figure. The bold solid lines A indicate the state in which the xcfx86H1 is at a low level, xcfx86H2 is at a high level, and xcfx86R is at a low level. In contrast, the thin line B in the figure indicates the state in which the xcfx86H1 is at a high level, xcfx86H2 is at a low level, and xcfx86R is at a high level; thus, the signal charge stored in the floating diffusion layer 115 is discharged through the reset gate electrode 116 to the reset drain 117. Simultaneously, the signal charge for the next bit stored in the previous stage is transferred to the horizontal terminal electrode portion.
The variation of the channel potential due to the horizontal driving pulse is equivalent to a sum of xcex94V1 and xcex94V2, shown in FIG. 10. The xcex94V1 represents the channel potential difference between the lower side of the storage electrodes 112b, 112c, 112d, . . . and the lower side of the barrier electrodes 113b, 113c, 113d, . . . when the same pulse is input. In contrast, the xcex94V2 represents the channel potential difference between the lower sides of the storage electrodes 112b, 112c, 112d, . . . and the lower side of the barrier electrodes 113b, 113c, 113d, . . . when a different pulse is input.
The charge transfer efficiency increases when the values of both xcex94V1 and xcex94V2 increase. However, since it is desirable to reduce the voltage in order to reduce the power consumption, both values of the xcex94V1 and xcex94V2 are reduced to lower values. The xcex94V3 is a channel potential difference of the horizontal terminal electrode portion between the lower sides of the storage electrode 112a and the barrier electrodes 113a. 
If the short channel effect or the narrow channel effect is neglected, the xcex94V1 and xcex94V3 are determined by the impurity concentration between the nxe2x88x92-type semiconductor regions 126a, 126b, 126c, . . . and an nxe2x88x92-type semiconductor well 121, and it is desirable that the xcex94V1 and xcex94V3 are the same. However, practically, because of the narrow channel effect by narrowing the channel width as described above, the xcex94V3 is lower by 0.1 to 0.3 V below the xcex94V1. That is, in the horizontal terminal electrode portion, the electric field between the storage electrode and the barrier electrode, to which the same pulse is applied, becomes weaker than that of the general horizontal transfer electrode portion, so that the transfer efficiency decreases at the terminal electrode portion. Especially when the driving pulse amplitude is reduced to a level of 3.3 V for reducing the power consumption, the xcex94V1 is reduced to a level as small as 1.0 V to 1.5 V and the xcex94V3 becomes smaller than the xcex94V1 value by 0.1 to 0.3 V, which causes the problem that the degradation of the transfer efficiency becomes more remarkable.
A method to prevent the degradation of the transfer efficiency in the vicinity of the horizontal terminal electrode portion is disclosed in Japanese Unexamined Patent Application, First publication No. Hei 9-252106. In this method, the storage electrode and the barrier electrode of the horizontal terminal electrode portion are unified into one electrode and then the storage region and the barrier region are divided by locally changing the impurity concentrations in a layer below the unified electrode. This measure has the effect that the pinning phenomenon of the channel potential by excess impurity injection can be prevented, since it is possible to eliminate, before formation of the horizontal transfer electrode, the channel used for potential adjustment of the entire horizontal CCD register and the process for the ion injection of the opposite conductive type ions. However, even in this method, the same problem still remains as that shown in the above Japanese Unexamined Patent Application, First Publication No. Hei 11-17613, because the process for providing the impurity concentration difference in these regions below the storage electrode and the barrier electrode is the same as the process for forming the horizontal transfer electrode portion and the horizontal terminal electrode portion.
The other method for improving the transfer efficiency in the vicinity of the horizontal terminal electrode portion is disclosed in Japanese Unexamined Patent Application, First Publication No. 5-55539. In this method, the storage electrode and the barrier electrode in the horizontal terminal electrode portion are unified into a first layer of a polycrytalline silicon gate electrode and the output gate electrode is constituted by forming a second polycrystalline silicon layer so that the impurity injection is performed on the lower portion of the output gate electrode in a self-aligning manner with the edge of the first layer of the polycrystalline silicon gate electrode. This method has the effect that the channel potential below the output gate electrode can be independently adjusted by changing the amount of impurity implantation.
However, the above-described method provides two layers consisting of a layer as a channel for the potential adjustment of the entire horizontal CCD register and a layer with the opposite conduction type, and the channel potential difference between the storage terminal region and the barrier terminal region of the horizontal terminal electrode portion is determined by the amount of impurity implantation and the location of the boundary of these two regions. Thus, the problem arises that there are many restrictions in determining the channel potential difference, and, since the impurity injection edge is determined by visual observation, the effective length of the barrier region in the charge transfer direction disperses, which may affect the channel potential difference between the storage region and the barrier region.
The present invention was made to solve above-described problems and an object of the present invention is to provide charge transfer devices having high charge transfer efficiency, low variation of the quality in the manufacturing process, and also a large freedom in designing the charge transfer devices.
The first aspect of the present invention provides a charge transfer device, which is provided with a plurality of pairs of charge transfer electrodes composed of an output gate electrode and a plurality of storage electrodes and barrier electrodes formed on a first conduction-type semiconductor layer, and a signal charge is transferred by applying a two phase driving pulse to said transfer electrodes, wherein a charge transfer electric field in a channel below a boundary portion between a terminal storage electrode and a terminal barrier electrode, which constitute a pair of charge transfer electrodes located closest to the output electrode, is set higher than a charge transfer electric field in a channel below a boundary portions of pairs of storage electrodes and barrier electrodes, which constitute pairs of storage electrodes and barrier electrodes other than the pair of the terminal electrodes.
In the above charge transfer device, said first conduction-type semiconductor layer corresponds to either one of a first conduction-type well layer formed on a second conduction-type semiconductor substrate or a first conduction-type semiconductor substrate.
In the above charge transfer device, a difference between the charge transfer electric field in a channel below a boundary portion between a terminal storage electrode and a terminal barrier electrode, which constitute a pair of charge transfer electrodes located closest to the output electrode, and the electric field for the charge transfer in a channel below a boundary portions of pairs of storage electrodes and barrier electrodes, which constitute pairs of storage electrodes and barrier electrodes other than the pair of the terminal electrodes, is formed by the difference in the impurity concentrations injected in respective boundary portions.
In the above charge transfer device, the impurity ions in the channel under the terminal storage electrode for forming the difference between the impurity concentrations is injected in a self-aligning manner with the insulating films formed at the side surfaces of the terminal barrier electrode and the output gate electrode.
The present invention includes a solid image pickup apparatus comprising the above-described charge transfer devices.